Conventionally, in this sort of hierarchical design, having been adopted is a method of dividing a target circuit to be designed into a plurality of partial circuits (referred to as blocks, or hierarchical blocks, hereinafter), designing the individual blocks, and then integrating these blocks into one, to thereby complete the entire design. By virtue of such divide-and-conquer design, the hierarchical design technique successfully raises an effect of realizing design of a large-scale integrated circuit, which is difficult in batch processing and batch optimization, in an efficient manner, while needing only a small memory consumption and short period of time. Examples of the conventional hierarchical design device are described in Patent Document 1 and Patent Document 2 (Japanese Laid-Open Patent Publication No. 2004-192227 and Japanese Laid-Open Patent Publication No. 2004-302819).
A processing for solving a problem in the hierarchical design, based on division, will be explained referring to FIG. 8.
An example shown in FIG. 8 relates to a processing carried out in the hierarchical design of a hierarchical block 1 (8-01) and a hierarchical block 2 (8-02) having gates 8-06, wherein generation and positional determination of boundary terminals 8-03 (hierarchical block terminals) on the boundaries of the hierarchical blocks are necessary. This is a processing for allowing independent execution of an intra-hierarchical-block layout 8-04 and an inter-hierarchical-block layout (8-05). Examples of devices for placing the hierarchical block terminals are described in Patent Document 3, Patent Document 4, Patent Document 5, and Patent Document 6 (Japanese Laid-Open Patent Publication No. 2000-67102, Japanese Laid-Open Patent Publication No. 2001-210717, Japanese Laid-Open Patent Publication No. 2002-215704, and Published Japanese Translation of PCT International Publication for Patent Application No. 2005-517223).
Now, for the purpose of improving efficiency in designing, the design of large-scale circuits is realized often by repetitively using the blocks having the same function at a plurality of sites in a chip. At what point of time in the designing the plurality of blocks having the same function are independently handled as different targets of design may variable, depending on the design technique, where the conventional hierarchical design technique may representatively be classified into two categories below.
1. Bottom-Up Hierarchical Design Technique: a single type of design is applied before the intra-block layout design, and in the step of placing the blocks on a chip, a common layout pattern is replicated at the individual sites where the blocks are used. In other words, a preliminarily-designed common layout pattern is used for a plurality of functional blocks. In this case, the positions of the block terminals are determined, taking designs of place-and-route inside the blocks into consideration.
2. Top-Down Hierarchical Design Technique: a single type of design is applied before the functional or logic design, the blocks having the same function are replicated in the step of intra-block layout design, and each of which is independently designed. In other words, different layout patterns are used respectively for a plurality the functional blocks having the same function. In this case, the positions of the block terminals are determined, after the blocks are placed on a chip, taking situation around the blocks into consideration.
The bottom-up hierarchical design method will be explained referring to FIG. 9. “A1 and A2”, and “B1 and B2” are sets of the functional blocks respectively having the same function.
In the bottom-up hierarchical design, in a first stage 9-03, internal layout designs are executed for every block 9-01 (hierarchical block). The internal layout designs include determination of positions of terminals 9-02 on the block boundary (hierarchical block terminals), and place-and-route determination in the block, wherein any block having internal layout design completed therein is assumed as a designed block. In this case, targets of the intra-block layout design are four blocks of A, B, C and D. Positions of the boundary input and output terminals of the individual blocks 9-01 are determined so that place-and-route design of the internal of the blocks 9-01 may be optimized.
Next, in a second stage 9-04, blocks having the same function are replicated (in this example, A is replicated to A1, A2, and B is replicated to B1, B2), the designed blocks are then placed on a chip (including determination of positions and directions of rotation), and inter-block routing 9-05 is executed there among.
Lastly, in a third stage 9-06, results of the first stage 9-03 and the second stage 9-04 are integrated, and thereby a chip layout is completed.
Next, the top-down hierarchical design will be explained referring to FIG. 10. Similarly to as in FIG. 9, “A1 and A2”, and “B1 and B2” are sets of the functional blocks respectively having the same function.
In the top-down hierarchical design method, first, in a first stage 10-03, an inter-block design is carried out. More specifically, after positions of blocks 10-01 on a chip are determined, positions of boundary input and output terminals (hierarchical block terminals) 10-02 of the individual blocks are determined so that routing among the blocks 10-01 (hierarchical blocks) may be optimized, to thereby complete the inter-block routing.
Next, in a second stage 10-04, the individual blocks are designed. In this step, under a fixed condition of the boundary input and output terminals of the blocks, layout design in each block is executed. Since “A1 and A2”, and “B1 and B2” are respectively differ in the positions of the input and output terminals, the same layout pattern is not adoptable to the same functional block sets. For this reason, the intra-block layout design is executed in 6 blocks of A1, A2, B1, B2, C and D.
Lastly, in a third stage 10-05, results of the first stage 10-03 and the second stage 10-04 are integrated, and thereby a chip layout is completed.    [Patent Document 1] Japanese Laid-Open Patent Publication No. 2004-192227    [Patent Document 2] Japanese Laid-Open Patent Publication No. 2004-302819    [Patent Document 3] Japanese Laid-Open Patent Publication No. 2000-67102    [Patent Document 4] Japanese Laid-Open Patent Publication No. 2001-210717    [Patent Document 5] Japanese Laid-Open Patent Publication No. 2002-215704    [Patent Document 6] Published Japanese Translation of PCT International Publication for Patent Application No. 2005-517223